34 #define QQQdialect MPLABX 48 #undef QQQMULTIPROCESSEXH 51 #define qqqMaxBranchDepth 20 52 #define QQQstructbitmap 64 #undef QQQTEMPLATEONLY 66 #define QQQUPLOADATEND 68 #undef QQQASHLINGVITRA 70 #define qqqbitmapint unsigned int 72 #undef QQQTIC2XSERIALIO 74 #undef QQQCOMPRESSED_EXH 81 #define hvps_test_67zzopen zzopen 83 #define hvps_test_67zqqzqz1 zqqzqz1 86 #define FILEPOINT FILE * f, 87 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 107 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 108 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 116 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 117 #ifndef LDRA_VOID_FUNC 118 #define LDRA_VOID_FUNC 121 #if defined(QQQMAINFL) 144 #ifdef QQQ_KEEPCOMMENTS 152 #if !defined(QQQSUPPRESS_UNDEF) 158 #undef QQQHITMAP_STORAGE 160 #define qqnull_params void 161 #define QQQ_PROTOTYPE_DEF 163 #undef QQ_ANSI_PROTOTYPE 165 #define QQ_ANSI_PROTOTYPE 1 168 #define QQ_ANSI_PROTOTYPE 1 174 #define ELEMENT(N) qqqbitmapint element##N; 176 #include "hvps_test_67zbelem.def" 180 #define ELEMENT(N) 0, 182 #include "hvps_test_67zbelem.def" 253 #ifndef _SYS_DEFINITIONS_H 254 #define _SYS_DEFINITIONS_H 263 #include "system/common/sys_common.h" 264 #include "system/common/sys_module.h" 348 #ifndef _SYSTEM_CONFIG_H 349 #define _SYSTEM_CONFIG_H 368 #define SYS_VERSION_STR "2.06" 369 #define SYS_VERSION 20600 373 #define SYS_CLK_FREQ 200000000ul 374 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 375 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 376 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 377 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 378 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 379 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 380 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 381 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 382 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 384 #define SYS_PORT_A_ANSEL 0x3F00 385 #define SYS_PORT_A_TRIS 0xFFED 386 #define SYS_PORT_A_LAT 0x0010 387 #define SYS_PORT_A_ODC 0x0000 388 #define SYS_PORT_A_CNPU 0x0020 389 #define SYS_PORT_A_CNPD 0x0000 390 #define SYS_PORT_A_CNEN 0x0021 391 #define SYS_PORT_B_ANSEL 0x10C8 392 #define SYS_PORT_B_TRIS 0x91FF 393 #define SYS_PORT_B_LAT 0x0000 394 #define SYS_PORT_B_ODC 0x0000 395 #define SYS_PORT_B_CNPU 0x0000 396 #define SYS_PORT_B_CNPD 0x0000 397 #define SYS_PORT_B_CNEN 0x0000 398 #define SYS_PORT_C_ANSEL 0xCFE1 399 #define SYS_PORT_C_TRIS 0xFFFF 400 #define SYS_PORT_C_LAT 0x0000 401 #define SYS_PORT_C_ODC 0x0000 402 #define SYS_PORT_C_CNPU 0x0000 403 #define SYS_PORT_C_CNPD 0x0000 404 #define SYS_PORT_C_CNEN 0x0000 405 #define SYS_PORT_D_ANSEL 0xC100 406 #define SYS_PORT_D_TRIS 0xFFFF 407 #define SYS_PORT_D_LAT 0x0000 408 #define SYS_PORT_D_ODC 0x0000 409 #define SYS_PORT_D_CNPU 0x0000 410 #define SYS_PORT_D_CNPD 0x0000 411 #define SYS_PORT_D_CNEN 0x0000 412 #define SYS_PORT_E_ANSEL 0xFC00 413 #define SYS_PORT_E_TRIS 0xFDFF 414 #define SYS_PORT_E_LAT 0x0000 415 #define SYS_PORT_E_ODC 0x0000 416 #define SYS_PORT_E_CNPU 0x0000 417 #define SYS_PORT_E_CNPD 0x0000 418 #define SYS_PORT_E_CNEN 0x0000 419 #define SYS_PORT_F_ANSEL 0xCEC0 420 #define SYS_PORT_F_TRIS 0xEFFF 421 #define SYS_PORT_F_LAT 0x0000 422 #define SYS_PORT_F_ODC 0x0000 423 #define SYS_PORT_F_CNPU 0x0000 424 #define SYS_PORT_F_CNPD 0x0000 425 #define SYS_PORT_F_CNEN 0x0000 426 #define SYS_PORT_G_ANSEL 0x8CBC 427 #define SYS_PORT_G_TRIS 0xDFFF 428 #define SYS_PORT_G_LAT 0x0000 429 #define SYS_PORT_G_ODC 0x0000 430 #define SYS_PORT_G_CNPU 0x0000 431 #define SYS_PORT_G_CNPD 0x0000 432 #define SYS_PORT_G_CNEN 0x0000 433 #define SYS_PORT_H_ANSEL 0x0070 434 #define SYS_PORT_H_TRIS 0xB3FB 435 #define SYS_PORT_H_LAT 0x0000 436 #define SYS_PORT_H_ODC 0x0000 437 #define SYS_PORT_H_CNPU 0x0000 438 #define SYS_PORT_H_CNPD 0x0000 439 #define SYS_PORT_H_CNEN 0x0000 440 #define SYS_PORT_J_ANSEL 0x0000 441 #define SYS_PORT_J_TRIS 0x8B7F 442 #define SYS_PORT_J_LAT 0x0080 443 #define SYS_PORT_J_ODC 0x0000 444 #define SYS_PORT_J_CNPU 0x0000 445 #define SYS_PORT_J_CNPD 0x0000 446 #define SYS_PORT_J_CNEN 0x0800 447 #define SYS_PORT_K_ANSEL 0xFF00 448 #define SYS_PORT_K_TRIS 0xFFFF 449 #define SYS_PORT_K_LAT 0x0000 450 #define SYS_PORT_K_ODC 0x0000 451 #define SYS_PORT_K_CNPU 0x0000 452 #define SYS_PORT_K_CNPD 0x0000 453 #define SYS_PORT_K_CNEN 0x0000 457 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 458 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 459 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 460 #define SYS_TMR_FREQUENCY 1000 461 #define SYS_TMR_FREQUENCY_TOLERANCE 10 462 #define SYS_TMR_UNIT_RESOLUTION 10000 463 #define SYS_TMR_CLIENT_TOLERANCE 10 464 #define SYS_TMR_INTERRUPT_NOTIFICATION false 470 #define DRV_IC_DRIVER_MODE_STATIC 473 #define DRV_SPI_NUMBER_OF_MODULES 6 476 #define DRV_SPI_POLLED 1 477 #define DRV_SPI_ISR 0 478 #define DRV_SPI_MASTER 1 479 #define DRV_SPI_SLAVE 0 481 #define DRV_SPI_EBM 1 482 #define DRV_SPI_8BIT 1 483 #define DRV_SPI_16BIT 1 484 #define DRV_SPI_32BIT 0 485 #define DRV_SPI_DMA 0 487 #define DRV_SPI_INSTANCES_NUMBER 3 488 #define DRV_SPI_CLIENTS_NUMBER 3 489 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 491 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 492 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 493 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 494 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 495 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 496 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 497 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 498 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 499 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 500 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 501 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 502 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 503 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 504 #define DRV_SPI_BAUD_RATE_IDX0 1000000 505 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 506 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 507 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 508 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 509 #define DRV_SPI_QUEUE_SIZE_IDX0 10 510 #define DRV_SPI_RESERVED_JOB_IDX0 1 512 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 513 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 514 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 515 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 516 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 517 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 518 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 519 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 520 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 521 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 522 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 523 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 524 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 525 #define DRV_SPI_BAUD_RATE_IDX1 1000000 526 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 527 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 528 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 529 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 530 #define DRV_SPI_QUEUE_SIZE_IDX1 10 531 #define DRV_SPI_RESERVED_JOB_IDX1 1 533 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 534 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 535 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 536 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 537 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 538 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 539 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 540 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 541 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 542 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 543 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 544 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 545 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 546 #define DRV_SPI_BAUD_RATE_IDX2 500000 547 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 548 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 549 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 550 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 551 #define DRV_SPI_QUEUE_SIZE_IDX2 10 552 #define DRV_SPI_RESERVED_JOB_IDX2 1 554 #define DRV_TMR_INTERRUPT_MODE true 556 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 557 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 558 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 559 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 560 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 561 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 562 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 563 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 564 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 565 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 566 #define DRV_TMR_POWER_STATE_IDX0 567 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 568 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 569 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 570 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 571 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 572 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 573 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 574 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 575 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 576 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 577 #define DRV_TMR_POWER_STATE_IDX1 579 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 580 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 581 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 582 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 583 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 584 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 585 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 586 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 587 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 588 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 589 #define DRV_TMR_POWER_STATE_IDX2 591 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 592 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 593 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 594 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 595 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 596 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 597 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 598 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 599 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 600 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 601 #define DRV_TMR_POWER_STATE_IDX3 603 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 604 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 605 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 606 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 607 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 608 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 609 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 610 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 611 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 612 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 613 #define DRV_TMR_POWER_STATE_IDX4 617 #define DRV_USART_INSTANCES_NUMBER 1 618 #define DRV_USART_CLIENTS_NUMBER 1 619 #define DRV_USART_INTERRUPT_MODE false 620 #define DRV_USART_BYTE_MODEL_SUPPORT true 621 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 622 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 630 #define DRV_USBHS_DEVICE_SUPPORT true 632 #define DRV_USBHS_HOST_SUPPORT false 634 #define DRV_USBHS_INSTANCES_NUMBER 1 636 #define DRV_USBHS_INTERRUPT_MODE true 638 #define DRV_USBHS_ENDPOINTS_NUMBER 2 641 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 643 #define USB_DEVICE_INSTANCES_NUMBER 1 645 #define USB_DEVICE_EP0_BUFFER_SIZE 64 647 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 655 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 656 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 657 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 658 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 659 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 661 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 662 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 663 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 664 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 665 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 667 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 668 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 669 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 670 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 671 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 673 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 674 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 675 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 676 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 677 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 679 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 680 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 681 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 682 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 683 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 685 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 686 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 687 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 688 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 689 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 691 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 692 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 693 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 694 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 695 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 697 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 698 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 699 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 700 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 701 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 703 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 704 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 705 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 706 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 707 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 709 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 710 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 711 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 712 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 713 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 715 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 716 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 717 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 718 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 719 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 721 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 722 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 723 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 724 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 725 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 727 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 728 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 729 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 730 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 731 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 733 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 734 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 735 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 736 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 737 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 739 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 740 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 741 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 742 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 743 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 745 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 746 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 747 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 748 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 749 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 751 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 752 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 753 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 754 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 755 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 757 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 758 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 759 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 760 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 761 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 763 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 764 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 765 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 766 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 767 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 769 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 771 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 773 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 775 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 777 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 779 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 781 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 783 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 785 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 787 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 789 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 791 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 793 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 795 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 797 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 799 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 801 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 802 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 803 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 804 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 805 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 806 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 807 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 856 #ifndef _DRV_COMMON_H 857 #define _DRV_COMMON_H 959 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 969 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 979 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1035 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1046 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1061 #define _PLIB_UNSUPPORTED 1069 #include "system/common/sys_module.h" 1081 #define DRV_IC_INDEX_0 0 1082 #define DRV_IC_INDEX_1 1 1083 #define DRV_IC_INDEX_2 2 1084 #define DRV_IC_INDEX_3 3 1085 #define DRV_IC_INDEX_4 4 1086 #define DRV_IC_INDEX_5 5 1087 #define DRV_IC_INDEX_6 6 1088 #define DRV_IC_INDEX_7 7 1089 #define DRV_IC_INDEX_8 8 1090 #define DRV_IC_INDEX_9 9 1091 #define DRV_IC_INDEX_10 10 1092 #define DRV_IC_INDEX_11 11 1093 #define DRV_IC_INDEX_12 12 1094 #define DRV_IC_INDEX_13 13 1095 #define DRV_IC_INDEX_14 14 1096 #define DRV_IC_INDEX_15 15 1128 const SYS_MODULE_INDEX index ,
1129 const SYS_MODULE_INIT *
const init ) ;
1151 const SYS_MODULE_INDEX drvIndex ,
1196 const SYS_MODULE_INDEX drvIndex ,
1329 #ifndef _DRV_IC_STATIC_H 1330 #define _DRV_IC_STATIC_H 1331 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1332 #define DRV_IC_Close( handle ) 1371 #include "system/devcon/sys_devcon.h" 1372 #include "system/clk/sys_clk.h" 1373 #include "system/int/sys_int.h" 1374 #include "system/tmr/sys_tmr.h" 1416 #ifndef _DRV_ADC_STATIC_H 1417 #define _DRV_ADC_STATIC_H 1418 #include <stdbool.h> 1419 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1420 #include "peripheral/adchs/plib_adchs.h" 1421 #include "peripheral/int/plib_int.h" 1461 uint8_t bufIndex ) ;
1465 uint8_t bufIndex ) ;
1515 #ifndef _DRV_TMR_STATIC_H 1516 #define _DRV_TMR_STATIC_H 1565 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1566 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1567 #include "peripheral/tmr/plib_tmr.h" 1603 #ifndef _TMR_DEFINITIONS_PIC32M_H 1604 #define _TMR_DEFINITIONS_PIC32M_H 1662 #include "system/int/sys_int.h" 1663 #include "system/clk/sys_clk.h" 1682 #define DRV_TMR_INDEX_0 0 1683 #define DRV_TMR_INDEX_1 1 1684 #define DRV_TMR_INDEX_2 2 1685 #define DRV_TMR_INDEX_3 3 1686 #define DRV_TMR_INDEX_4 4 1687 #define DRV_TMR_INDEX_5 5 1688 #define DRV_TMR_INDEX_6 6 1689 #define DRV_TMR_INDEX_7 7 1690 #define DRV_TMR_INDEX_8 8 1691 #define DRV_TMR_INDEX_9 9 1692 #define DRV_TMR_INDEX_10 10 1693 #define DRV_TMR_INDEX_11 11 1704 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1789 uint32_t dividerMin ;
1791 uint32_t dividerMax ;
1794 uint32_t dividerStep ;
1810 SYS_MODULE_INIT moduleInit ;
1812 TMR_MODULE_ID tmrId ;
1816 TMR_PRESCALE prescale ;
1820 INT_SOURCE interruptSource ;
1828 bool asyncWriteEnable ;
1843 uint32_t alarmCount ) ;
1905 const SYS_MODULE_INDEX drvIndex ,
1906 const SYS_MODULE_INIT *
const init ) ;
1946 SYS_MODULE_OBJ
object ) ;
1993 SYS_MODULE_OBJ
object ) ;
2027 SYS_MODULE_OBJ
object ) ;
2081 const SYS_MODULE_INDEX index ,
2182 uint32_t counterPeriod ) ;
2672 TMR_PRESCALE preScale ) ;
2912 #ifndef _DRV_TMR_DEPRECATED_H 2913 #define _DRV_TMR_DEPRECATED_H 2954 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3018 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3083 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3142 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3203 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3262 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3323 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3353 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3385 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3416 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3448 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3510 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3575 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3592 #include "peripheral/tmr/plib_tmr.h" 3593 #include "peripheral/int/plib_int.h" 3595 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3597 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3599 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3601 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3620 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3626 static inline SYS_STATUS
3629 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3640 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3651 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3661 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3670 TMR_PRESCALE prescale ) ;
3701 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3730 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3736 static inline SYS_STATUS
3739 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3750 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3761 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3771 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3780 TMR_PRESCALE prescale ) ;
3811 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3840 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3846 static inline SYS_STATUS
3849 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3860 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3871 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3881 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3890 TMR_PRESCALE prescale ) ;
3921 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3950 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3956 static inline SYS_STATUS
3959 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3970 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3981 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3991 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
4000 TMR_PRESCALE prescale ) ;
4031 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4060 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4066 static inline SYS_STATUS
4069 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4080 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4091 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4101 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4110 TMR_PRESCALE prescale ) ;
4141 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4160 #include "peripheral/int/plib_int.h" 4202 #ifndef _DRV_PMP_STATIC_H 4203 #define _DRV_PMP_STATIC_H 4204 #include "peripheral/pmp/plib_pmp.h" 4219 PMP_DATA_WAIT_STATES dataWait ,
4220 PMP_STROBE_WAIT_STATES strobeWait ,
4221 PMP_DATA_HOLD_STATES dataHold ) ;
4276 #ifndef _DRV_USART_STATIC_H 4277 #define _DRV_USART_STATIC_H 4316 #ifndef _DRV_USART_STATIC_LOCAL_H 4317 #define _DRV_USART_STATIC_LOCAL_H 4324 #include <stdbool.h> 4361 #ifndef _DRV_USART_H 4362 #define _DRV_USART_H 4402 #ifndef _DRV_USART_DEFINITIONS_H 4403 #define _DRV_USART_DEFINITIONS_H 4409 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4410 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4447 #ifndef _PLIB_USART_H 4448 #define _PLIB_USART_H 4491 #ifndef _USART_PROCESSOR_H 4492 #define _USART_PROCESSOR_H 4501 #include <stdbool.h> 4502 #error "No Processor Family specified" 4546 USART_MODULE_ID index ) ;
4576 USART_MODULE_ID index ) ;
4608 USART_MODULE_ID index ) ;
4642 USART_MODULE_ID index ,
4643 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4672 USART_BRG_CLOCK_SOURCE
4674 USART_MODULE_ID index ) ;
4728 USART_MODULE_ID index ) ;
4758 USART_MODULE_ID index ) ;
4787 USART_MODULE_ID index ) ;
4819 USART_MODULE_ID index ) ;
4850 USART_MODULE_ID index ) ;
4892 USART_MODULE_ID index ) ;
4925 USART_MODULE_ID index ) ;
4957 USART_MODULE_ID index ) ;
4998 USART_MODULE_ID index ,
4999 uint32_t clockFrequency ,
5000 uint32_t baudRate ) ;
5041 USART_MODULE_ID index ,
5042 uint32_t clockFrequency ,
5043 uint32_t baudRate ) ;
5076 USART_MODULE_ID index ,
5077 int32_t clockFrequency ) ;
5112 USART_MODULE_ID index ,
5147 USART_MODULE_ID index ) ;
5182 USART_MODULE_ID index ,
5217 USART_MODULE_ID index ) ;
5249 USART_MODULE_ID index ) ;
5283 USART_MODULE_ID index ) ;
5316 USART_MODULE_ID index ) ;
5349 USART_MODULE_ID index ) ;
5383 USART_MODULE_ID index ,
5428 USART_MODULE_ID index ) ;
5462 USART_MODULE_ID index ) ;
5498 USART_MODULE_ID index ) ;
5535 USART_MODULE_ID index ,
5575 USART_MODULE_ID index ) ;
5613 USART_MODULE_ID index ) ;
5648 USART_MODULE_ID index ) ;
5682 USART_MODULE_ID index ) ;
5716 USART_MODULE_ID index ) ;
5749 USART_MODULE_ID index ) ;
5781 USART_MODULE_ID index ) ;
5813 USART_MODULE_ID index ) ;
5846 USART_MODULE_ID index ) ;
5880 USART_MODULE_ID index ) ;
5909 USART_MODULE_ID index ) ;
5938 USART_MODULE_ID index ) ;
5970 USART_MODULE_ID index ) ;
6002 USART_MODULE_ID index ) ;
6032 USART_MODULE_ID index ) ;
6062 USART_MODULE_ID index ) ;
6091 USART_MODULE_ID index ) ;
6120 USART_MODULE_ID index ) ;
6154 USART_MODULE_ID index ,
6155 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6187 USART_MODULE_ID index ,
6188 USART_RECEIVE_INTR_MODE interruptMode ) ;
6221 USART_MODULE_ID index ,
6222 USART_LINECONTROL_MODE dataFlowConfig ) ;
6255 USART_MODULE_ID index ,
6256 USART_HANDSHAKE_MODE handshakeConfig ) ;
6289 USART_MODULE_ID index ,
6320 USART_MODULE_ID index ) ;
6349 USART_MODULE_ID index ) ;
6380 USART_MODULE_ID index ) ;
6411 USART_MODULE_ID index ) ;
6441 USART_MODULE_ID index ) ;
6473 USART_MODULE_ID index ,
6474 USART_OPERATION_MODE operationmode ) ;
6504 USART_MODULE_ID index ) ;
6537 USART_MODULE_ID index ) ;
6566 USART_MODULE_ID index ) ;
6596 USART_MODULE_ID index ) ;
6632 USART_MODULE_ID index ) ;
6683 USART_MODULE_ID index ,
6686 bool wakeFromSleep ,
6731 USART_MODULE_ID index ,
6732 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6733 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6734 USART_OPERATION_MODE operationMode ) ;
6780 USART_MODULE_ID index ,
6781 uint32_t systemClock ,
6827 USART_MODULE_ID index ) ;
6848 USART_MODULE_ID index ) ;
6869 USART_MODULE_ID index ) ;
6903 USART_MODULE_ID index ) ;
6930 USART_MODULE_ID index ) ;
6956 USART_MODULE_ID index ) ;
6983 USART_MODULE_ID index ) ;
7009 USART_MODULE_ID index ) ;
7034 USART_MODULE_ID index ) ;
7060 USART_MODULE_ID index ) ;
7085 USART_MODULE_ID index ) ;
7111 USART_MODULE_ID index ) ;
7136 USART_MODULE_ID index ) ;
7162 USART_MODULE_ID index ) ;
7189 USART_MODULE_ID index ) ;
7215 USART_MODULE_ID index ) ;
7241 USART_MODULE_ID index ) ;
7268 USART_MODULE_ID index ) ;
7295 USART_MODULE_ID index ) ;
7322 USART_MODULE_ID index ) ;
7348 USART_MODULE_ID index ) ;
7373 USART_MODULE_ID index ) ;
7399 USART_MODULE_ID index ) ;
7426 USART_MODULE_ID index ) ;
7452 USART_MODULE_ID index ) ;
7478 USART_MODULE_ID index ) ;
7503 USART_MODULE_ID index ) ;
7528 USART_MODULE_ID index ) ;
7553 USART_MODULE_ID index ) ;
7579 USART_MODULE_ID index ) ;
7604 USART_MODULE_ID index ) ;
7630 USART_MODULE_ID index ) ;
7656 USART_MODULE_ID index ) ;
7681 USART_MODULE_ID index ) ;
7707 USART_MODULE_ID index ) ;
7732 USART_MODULE_ID index ) ;
7757 USART_MODULE_ID index ) ;
7784 USART_MODULE_ID index ) ;
7809 USART_MODULE_ID index ) ;
7835 USART_MODULE_ID index ) ;
7900 #include "system/common/sys_common.h" 7901 #include "system/common/sys_module.h" 7913 #include "system/int/sys_int.h" 7985 #ifndef _SYS_DMA_DEFINITIONS_H 7986 #define _SYS_DMA_DEFINITIONS_H 7992 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7993 #include "system/common/sys_common.h" 7994 #include "system/common/sys_module.h" 8064 #ifndef _PLIB_DMA_PROCESSOR_H 8065 #define _PLIB_DMA_PROCESSOR_H 8066 #error "Can't find header" 8110 DMA_MODULE_ID index ,
8111 DMA_CHANNEL channel ) ;
8145 DMA_MODULE_ID index ,
8146 DMA_CHANNEL channel ,
8147 DMA_CHANNEL_COLLISION collisonType ) ;
8179 DMA_MODULE_ID index ,
8180 DMA_CHANNEL channel ) ;
8212 DMA_MODULE_ID index ,
8213 DMA_CHANNEL channel ) ;
8251 DMA_MODULE_ID index ,
8252 DMA_CHANNEL channel ,
8253 DMA_CHANNEL_PRIORITY channelPriority ) ;
8282 DMA_CHANNEL_PRIORITY
8284 DMA_MODULE_ID index ,
8285 DMA_CHANNEL channel ) ;
8313 DMA_MODULE_ID index ,
8314 DMA_CHANNEL_PRIORITY channelPriority ) ;
8339 DMA_CHANNEL_PRIORITY
8341 DMA_MODULE_ID index ) ;
8371 DMA_MODULE_ID index ,
8372 DMA_CHANNEL channel ) ;
8403 DMA_MODULE_ID index ,
8404 DMA_CHANNEL channel ) ;
8433 DMA_MODULE_ID index ,
8434 DMA_CHANNEL channel ) ;
8463 DMA_MODULE_ID index ,
8464 DMA_CHANNEL channel ) ;
8495 DMA_MODULE_ID index ,
8496 DMA_CHANNEL channel ) ;
8525 DMA_MODULE_ID index ,
8526 DMA_CHANNEL channel ) ;
8557 DMA_MODULE_ID index ,
8558 DMA_CHANNEL channel ) ;
8589 DMA_MODULE_ID index ,
8590 DMA_CHANNEL channel ) ;
8619 DMA_MODULE_ID index ,
8620 DMA_CHANNEL channel ) ;
8651 DMA_MODULE_ID index ,
8652 DMA_CHANNEL channel ) ;
8681 DMA_MODULE_ID index ,
8682 DMA_CHANNEL channel ) ;
8712 DMA_MODULE_ID index ,
8713 DMA_CHANNEL channel ) ;
8743 DMA_MODULE_ID index ,
8744 DMA_CHANNEL channel ) ;
8774 DMA_MODULE_ID index ,
8775 DMA_CHANNEL channel ) ;
8805 DMA_MODULE_ID index ,
8806 DMA_CHANNEL channel ) ;
8837 DMA_MODULE_ID index ,
8838 DMA_CHANNEL channel ) ;
8869 DMA_MODULE_ID index ,
8870 DMA_CHANNEL channel ,
8871 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8900 DMA_CHANNEL_TRANSFER_DIRECTION
8902 DMA_MODULE_ID index ,
8903 DMA_CHANNEL channel ) ;
8939 DMA_MODULE_ID index ,
8940 DMA_CHANNEL channel ,
8942 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8975 DMA_MODULE_ID index ,
8976 DMA_CHANNEL channel ,
8977 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9008 DMA_MODULE_ID index ,
9009 DMA_CHANNEL channel ,
9010 uint16_t peripheraladdress ) ;
9038 DMA_MODULE_ID index ,
9039 DMA_CHANNEL channel ) ;
9070 DMA_MODULE_ID index ,
9071 DMA_CHANNEL channel ,
9072 uint16_t transferCount ) ;
9100 DMA_MODULE_ID index ,
9101 DMA_CHANNEL channel ) ;
9134 DMA_MODULE_ID index ,
9135 DMA_CHANNEL channel ,
9136 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9164 DMA_SOURCE_ADDRESSING_MODE
9166 DMA_MODULE_ID index ,
9167 DMA_CHANNEL channel ) ;
9200 DMA_MODULE_ID index ,
9201 DMA_CHANNEL channel ,
9202 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9231 DMA_DESTINATION_ADDRESSING_MODE
9233 DMA_MODULE_ID index ,
9234 DMA_CHANNEL channel ) ;
9267 DMA_MODULE_ID index ,
9268 DMA_CHANNEL channel ,
9269 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9297 DMA_CHANNEL_ADDRESSING_MODE
9299 DMA_MODULE_ID index ,
9300 DMA_CHANNEL channel ) ;
9338 DMA_MODULE_ID index ,
9339 DMA_CHANNEL channel ,
9340 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9376 DMA_MODULE_ID index ,
9377 DMA_CHANNEL channel ,
9378 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9413 DMA_MODULE_ID index ,
9414 DMA_CHANNEL channel ,
9415 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9444 DMA_CHANNEL_INT_SOURCE
9446 DMA_MODULE_ID index ,
9447 DMA_CHANNEL channel ) ;
9482 DMA_MODULE_ID index ,
9483 DMA_CHANNEL channel ,
9484 DMA_TRIGGER_SOURCE IRQnum ) ;
9519 DMA_MODULE_ID index ,
9520 DMA_CHANNEL channel ,
9521 DMA_TRIGGER_SOURCE IRQ ) ;
9552 DMA_MODULE_ID index ,
9553 DMA_CHANNEL channel ,
9554 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9581 DMA_CHANNEL_DATA_SIZE
9583 DMA_MODULE_ID index ,
9584 DMA_CHANNEL channel ) ;
9618 DMA_MODULE_ID index ,
9619 DMA_CHANNEL channel ,
9620 DMA_TRANSFER_MODE channeltransferMode ) ;
9652 DMA_MODULE_ID index ,
9653 DMA_CHANNEL channel ) ;
9682 DMA_MODULE_ID index ,
9683 DMA_CHANNEL channel ) ;
9713 DMA_MODULE_ID index ,
9714 DMA_CHANNEL channel ) ;
9743 DMA_MODULE_ID index ,
9744 DMA_CHANNEL channel ) ;
9772 DMA_MODULE_ID index ,
9773 DMA_CHANNEL channel ) ;
9803 DMA_MODULE_ID index ,
9804 DMA_CHANNEL channel ) ;
9831 DMA_MODULE_ID index ,
9832 DMA_CHANNEL channel ) ;
9868 DMA_MODULE_ID index ,
9869 DMA_CHANNEL channel ) ;
9900 DMA_MODULE_ID index ,
9901 DMA_CHANNEL channel ) ;
9934 DMA_MODULE_ID index ) ;
9963 DMA_MODULE_ID index ) ;
9993 DMA_MODULE_ID index ) ;
10022 DMA_MODULE_ID index ) ;
10051 DMA_MODULE_ID index ) ;
10081 DMA_MODULE_ID index ) ;
10109 DMA_MODULE_ID index ) ;
10137 DMA_MODULE_ID index ) ;
10165 DMA_MODULE_ID index ) ;
10194 DMA_MODULE_ID index ) ;
10222 DMA_MODULE_ID index ) ;
10256 DMA_MODULE_ID index ) ;
10286 DMA_MODULE_ID index ) ;
10316 DMA_MODULE_ID index ) ;
10345 DMA_MODULE_ID index ) ;
10380 DMA_MODULE_ID index ,
10381 DMA_CHANNEL channel ) ;
10410 DMA_MODULE_ID index ) ;
10442 DMA_MODULE_ID index ,
10443 DMA_CRC_TYPE CRCType ) ;
10474 DMA_MODULE_ID index ) ;
10504 DMA_MODULE_ID index ) ;
10534 DMA_MODULE_ID index ) ;
10564 DMA_MODULE_ID index ) ;
10593 DMA_MODULE_ID index ) ;
10623 DMA_MODULE_ID index ) ;
10652 DMA_MODULE_ID index ) ;
10682 DMA_MODULE_ID index ,
10683 uint8_t polyLength ) ;
10712 DMA_MODULE_ID index ) ;
10741 DMA_MODULE_ID index ,
10742 DMA_CRC_BIT_ORDER bitOrder ) ;
10773 DMA_MODULE_ID index ) ;
10802 DMA_MODULE_ID index ) ;
10832 DMA_MODULE_ID index ,
10833 DMA_CRC_BYTE_ORDER byteOrder ) ;
10862 DMA_MODULE_ID index ) ;
10893 DMA_MODULE_ID index ) ;
10925 DMA_MODULE_ID index ,
10926 uint32_t DMACRCdata ) ;
10957 DMA_MODULE_ID index ) ;
10990 DMA_MODULE_ID index ,
10991 uint32_t DMACRCXOREnableMask ) ;
11029 DMA_MODULE_ID index ,
11030 DMA_CHANNEL dmaChannel ) ;
11067 DMA_MODULE_ID index ,
11068 DMA_CHANNEL dmaChannel ,
11069 uint32_t sourceStartAddress ) ;
11103 DMA_MODULE_ID index ,
11104 DMA_CHANNEL dmaChannel ) ;
11142 DMA_MODULE_ID index ,
11143 DMA_CHANNEL dmaChannel ,
11144 uint32_t destinationStartAddress ) ;
11184 DMA_MODULE_ID index ,
11185 DMA_CHANNEL dmaChannel ) ;
11224 DMA_MODULE_ID index ,
11225 DMA_CHANNEL dmaChannel ,
11226 uint16_t sourceSize ) ;
11261 DMA_MODULE_ID index ,
11262 DMA_CHANNEL dmaChannel ) ;
11299 DMA_MODULE_ID index ,
11300 DMA_CHANNEL dmaChannel ,
11301 uint16_t destinationSize ) ;
11335 DMA_MODULE_ID index ,
11336 DMA_CHANNEL dmaChannel ) ;
11371 DMA_MODULE_ID index ,
11372 DMA_CHANNEL dmaChannel ) ;
11407 DMA_MODULE_ID index ,
11408 DMA_CHANNEL dmaChannel ) ;
11445 DMA_MODULE_ID index ,
11446 DMA_CHANNEL dmaChannel ,
11447 uint16_t CellSize ) ;
11481 DMA_MODULE_ID index ,
11482 DMA_CHANNEL dmaChannel ) ;
11519 DMA_MODULE_ID index ,
11520 DMA_CHANNEL dmaChannel ) ;
11559 DMA_MODULE_ID index ,
11560 DMA_CHANNEL dmaChannel ,
11561 uint16_t patternData ) ;
11605 DMA_MODULE_ID index ,
11606 DMA_CHANNEL dmaChannel ,
11607 DMA_INT_TYPE dmaINTSource ) ;
11642 DMA_MODULE_ID index ,
11643 DMA_CHANNEL dmaChannel ,
11644 DMA_INT_TYPE dmaINTSource ) ;
11680 DMA_MODULE_ID index ,
11681 DMA_CHANNEL dmaChannel ,
11682 DMA_INT_TYPE dmaINTSource ) ;
11716 DMA_MODULE_ID index ,
11717 DMA_CHANNEL dmaChannel ,
11718 DMA_INT_TYPE dmaINTSource ) ;
11752 DMA_MODULE_ID index ,
11753 DMA_CHANNEL dmaChannel ,
11754 DMA_INT_TYPE dmaINTSource ) ;
11792 DMA_MODULE_ID index ,
11793 DMA_CHANNEL dmaChannel ,
11794 DMA_INT_TYPE dmaINTSource ) ;
11827 DMA_MODULE_ID index ,
11828 DMA_CHANNEL dmaChannel ,
11829 DMA_PATTERN_LENGTH patternLen ) ;
11862 DMA_MODULE_ID index ,
11863 DMA_CHANNEL dmaChannel ) ;
11893 DMA_MODULE_ID index ,
11894 DMA_CHANNEL channel ) ;
11927 DMA_MODULE_ID index ,
11928 DMA_CHANNEL channel ) ;
11958 DMA_MODULE_ID index ,
11959 DMA_CHANNEL channel ) ;
11991 DMA_MODULE_ID index ,
11992 DMA_CHANNEL channel ,
11993 uint8_t pattern ) ;
12024 DMA_MODULE_ID index ,
12025 DMA_CHANNEL channel ) ;
12057 DMA_MODULE_ID index ) ;
12082 DMA_MODULE_ID index ) ;
12106 DMA_MODULE_ID index ) ;
12131 DMA_MODULE_ID index ) ;
12154 DMA_MODULE_ID index ) ;
12178 DMA_MODULE_ID index ) ;
12201 DMA_MODULE_ID index ) ;
12225 DMA_MODULE_ID index ) ;
12249 DMA_MODULE_ID index ) ;
12274 DMA_MODULE_ID index ) ;
12298 DMA_MODULE_ID index ) ;
12322 DMA_MODULE_ID index ) ;
12345 DMA_MODULE_ID index ) ;
12369 DMA_MODULE_ID index ) ;
12393 DMA_MODULE_ID index ) ;
12417 DMA_MODULE_ID index ) ;
12441 DMA_MODULE_ID index ) ;
12465 DMA_MODULE_ID index ) ;
12488 DMA_MODULE_ID index ) ;
12513 DMA_MODULE_ID index ) ;
12538 DMA_MODULE_ID index ) ;
12562 DMA_MODULE_ID index ) ;
12587 DMA_MODULE_ID index ) ;
12611 DMA_MODULE_ID index ) ;
12635 DMA_MODULE_ID index ) ;
12661 DMA_MODULE_ID index ) ;
12686 DMA_MODULE_ID index ) ;
12710 DMA_MODULE_ID index ) ;
12735 DMA_MODULE_ID index ) ;
12758 DMA_MODULE_ID index ) ;
12781 DMA_MODULE_ID index ) ;
12804 DMA_MODULE_ID index ) ;
12827 DMA_MODULE_ID index ) ;
12852 DMA_MODULE_ID index ) ;
12877 DMA_MODULE_ID index ) ;
12901 DMA_MODULE_ID index ) ;
12926 DMA_MODULE_ID index ) ;
12950 DMA_MODULE_ID index ) ;
12974 DMA_MODULE_ID index ) ;
12997 DMA_MODULE_ID index ) ;
13020 DMA_MODULE_ID index ) ;
13044 DMA_MODULE_ID index ) ;
13068 DMA_MODULE_ID index ) ;
13092 DMA_MODULE_ID index ) ;
13119 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13132 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13145 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13175 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13349 DMA_CRC_TYPE type ;
13355 uint8_t polyLength ;
13358 DMA_CRC_BIT_ORDER bitOrder ;
13361 DMA_CRC_BYTE_ORDER byteOrder ;
13371 uint32_t xorBitMask ;
13496 SYS_MODULE_OBJ
object ,
13497 DMA_CHANNEL activeChannel ) ;
13500 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13545 uintptr_t contextHandle ) ;
13591 const SYS_MODULE_INIT *
const init ) ;
13642 DMA_CHANNEL channel ) ;
13728 DMA_TRIGGER_SOURCE eventSrc ) ;
13806 DMA_PATTERN_LENGTH length ,
13808 uint8_t ignorePattern ) ;
14061 const void * srcAddr ,
14063 const void * destAddr ,
14065 size_t cellSize ) ;
14162 const void * srcAddr ,
14164 const void * destAddr ,
14166 size_t cellSize ) ;
14362 const uintptr_t contextHandle ) ;
14658 DMA_TRIGGER_SOURCE eventSrc ) ;
14837 SYS_MODULE_OBJ
object ,
14838 DMA_CHANNEL activeChannel ) ;
14848 SYS_MODULE_OBJ
object ) ;
14858 SYS_MODULE_OBJ
object ,
14859 DMA_CHANNEL activeChannel ) ;
14886 #define DRV_USART_INDEX_0 0 14887 #define DRV_USART_INDEX_1 1 14888 #define DRV_USART_INDEX_2 2 14889 #define DRV_USART_INDEX_3 3 14890 #define DRV_USART_INDEX_4 4 14891 #define DRV_USART_INDEX_5 5 14905 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14916 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14927 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14961 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15112 uintptr_t context ) ;
15160 USART_HANDSHAKE_MODE_FLOW_CONTROL
15164 USART_HANDSHAKE_MODE_SIMPLEX
15326 } AddressedModeInit ;
15351 = USART_ERROR_PARITY
15356 = USART_ERROR_FRAMING
15361 = USART_ERROR_RECEIVER_OVERRUN
15443 SYS_MODULE_INIT moduleInit ;
15447 USART_MODULE_ID usartID ;
15465 uint32_t brgClock ;
15481 USART_OPERATION_MODE linesEnable ;
15485 INT_SOURCE interruptTransmit ;
15489 INT_SOURCE interruptReceive ;
15493 INT_SOURCE interruptError ;
15498 unsigned int queueSizeReceive ;
15503 unsigned int queueSizeTransmit ;
15507 DMA_CHANNEL dmaChannelTransmit ;
15511 DMA_CHANNEL dmaChannelReceive ;
15515 INT_SOURCE dmaInterruptTransmit ;
15519 INT_SOURCE dmaInterruptReceive ;
15603 const SYS_MODULE_INDEX index ,
15604 const SYS_MODULE_INIT *
const init ) ;
15642 SYS_MODULE_OBJ
object ) ;
15680 SYS_MODULE_OBJ
object ) ;
15721 SYS_MODULE_OBJ
object ) ;
15762 SYS_MODULE_OBJ
object ) ;
15803 SYS_MODULE_OBJ
object ) ;
15882 const SYS_MODULE_INDEX index ,
16066 const size_t size ) ;
16259 const size_t size ) ;
16347 const uintptr_t context ) ;
16614 const size_t numbytes ) ;
16682 const size_t numbytes ) ;
16819 const uint8_t byte ) ;
17037 const SYS_MODULE_INDEX index ,
17090 const SYS_MODULE_INDEX index ,
17139 const SYS_MODULE_INDEX index ,
17354 #ifndef _DRV_USART_FEATURE_MAPPING_H 17355 #define _DRV_USART_FEATURE_MAPPING_H 17364 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17365 #define _DRV_USART_InterruptSourceEnable( source ) 17366 #define _DRV_USART_InterruptSourceDisable( source ) false 17367 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17368 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17369 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17370 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17371 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17374 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17383 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17384 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17385 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17386 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17387 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17400 #include "system/clk/sys_clk.h" 17401 #include "system/int/sys_int.h" 17439 #ifndef _SYS_DEBUG_H 17440 #define _SYS_DEBUG_H 17441 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17444 #define SYS_DEBUG_BUFFER_DMA_READY 17494 #define SYS_DEBUG_INDEX_0 0 17510 SYS_MODULE_INIT moduleInit ;
17514 SYS_MODULE_INDEX consoleIndex ;
17562 const SYS_MODULE_INDEX index ,
17563 const SYS_MODULE_INIT *
const init ) ;
17603 SYS_MODULE_OBJ
object ,
17604 const SYS_MODULE_INIT *
const init ) ;
17634 SYS_MODULE_OBJ
object ) ;
17667 SYS_MODULE_OBJ
object ) ;
17711 SYS_MODULE_OBJ
object ) ;
17754 const char * message ) ;
17804 const char * format ,
17894 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17938 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17981 #define SYS_MESSAGE( message ) 18014 #define SYS_DEBUG_MESSAGE( level , message ) 18061 #define SYS_PRINT( fmt ,... ) 18109 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18134 #define SYS_DEBUG_BreakPoint( ) 18143 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18144 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18145 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18162 #define _DRV_USART_RX_DEPTH 9 18228 const SYS_MODULE_INDEX index ,
18253 const uint8_t byte ) ;
18324 #ifndef _SYS_PORTS_H 18325 #define _SYS_PORTS_H 18364 #ifndef _SYS_PORTS_DEFINITIONS_H 18365 #define _SYS_PORTS_DEFINITIONS_H 18371 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18372 #include "system/common/sys_common.h" 18373 #include "system/common/sys_module.h" 18410 #ifndef _PLIB_PORTS_H 18411 #define _PLIB_PORTS_H 18412 #include <stdint.h> 18413 #include <stddef.h> 18478 #ifndef _PLIB_PORTS_PROCESSOR_H 18479 #define _PLIB_PORTS_PROCESSOR_H 18480 #error "Can't find header" 18530 PORTS_MODULE_ID index ,
18531 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18532 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18575 PORTS_MODULE_ID index ,
18576 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18577 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18612 PORTS_MODULE_ID index ,
18613 PORTS_ANALOG_PIN pin ,
18614 PORTS_PIN_MODE mode ) ;
18654 PORTS_MODULE_ID index ,
18655 PORTS_CHANNEL channel ,
18656 PORTS_BIT_POS bitPos ,
18657 PORTS_PIN_MODE mode ) ;
18692 PORTS_MODULE_ID index ,
18693 PORTS_CHANNEL channel ,
18694 PORTS_BIT_POS bitPos ) ;
18728 PORTS_MODULE_ID index ,
18729 PORTS_CHANNEL channel ,
18730 PORTS_BIT_POS bitPos ) ;
18767 PORTS_MODULE_ID index ,
18768 PORTS_CHANNEL channel ,
18769 PORTS_BIT_POS bitPos ) ;
18810 PORTS_MODULE_ID index ,
18811 PORTS_CHANNEL channel ,
18812 PORTS_BIT_POS bitPos ) ;
18851 PORTS_MODULE_ID index ,
18852 PORTS_CHANNEL channel ,
18853 PORTS_BIT_POS bitPos ) ;
18891 PORTS_MODULE_ID index ,
18892 PORTS_CHANNEL channel ,
18893 PORTS_BIT_POS bitPos ) ;
18928 PORTS_MODULE_ID index ,
18929 PORTS_CHANNEL channel ) ;
18964 PORTS_MODULE_ID index ,
18965 PORTS_CHANNEL channel ) ;
19002 PORTS_MODULE_ID index ,
19003 PORTS_CHANNEL channel ) ;
19040 PORTS_MODULE_ID index ,
19041 PORTS_CHANNEL channel ) ;
19078 PORTS_MODULE_ID index ,
19079 PORTS_CHANNEL channel ,
19080 PORTS_BIT_POS bitPos ) ;
19117 PORTS_MODULE_ID index ,
19118 PORTS_CHANNEL channel ,
19119 PORTS_BIT_POS bitPos ) ;
19157 PORTS_MODULE_ID index ,
19158 PORTS_CHANNEL channel ,
19159 PORTS_BIT_POS bitPos ) ;
19196 PORTS_MODULE_ID index ,
19197 PORTS_CHANNEL channel ,
19198 PORTS_BIT_POS bitPos ,
19233 PORTS_MODULE_ID index ,
19234 PORTS_CHANNEL channel ,
19235 PORTS_BIT_POS bitPos ) ;
19269 PORTS_MODULE_ID index ,
19270 PORTS_CHANNEL channel ,
19271 PORTS_BIT_POS bitPos ) ;
19305 PORTS_MODULE_ID index ,
19306 PORTS_CHANNEL channel ,
19307 PORTS_BIT_POS bitPos ) ;
19342 PORTS_MODULE_ID index ,
19343 PORTS_CHANNEL channel ,
19344 PORTS_BIT_POS bitPos ) ;
19379 PORTS_MODULE_ID index ,
19380 PORTS_CHANNEL channel ,
19381 PORTS_BIT_POS bitPos ) ;
19415 PORTS_MODULE_ID index ,
19416 PORTS_CHANNEL channel ,
19417 PORTS_BIT_POS bitPos ) ;
19451 PORTS_MODULE_ID index ,
19452 PORTS_CHANNEL channel ,
19453 PORTS_BIT_POS bitPos ) ;
19491 PORTS_MODULE_ID index ,
19492 PORTS_CHANNEL channel ) ;
19526 PORTS_MODULE_ID index ,
19527 PORTS_CHANNEL channel ) ;
19561 PORTS_MODULE_ID index ,
19562 PORTS_CHANNEL channel ,
19605 PORTS_MODULE_ID index ,
19606 PORTS_CHANNEL channel ,
19642 PORTS_MODULE_ID index ,
19643 PORTS_CHANNEL channel ,
19678 PORTS_MODULE_ID index ,
19679 PORTS_CHANNEL channel ,
19715 PORTS_MODULE_ID index ,
19716 PORTS_CHANNEL channel ,
19751 PORTS_MODULE_ID index ,
19752 PORTS_CHANNEL channel ,
19785 PORTS_MODULE_ID index ,
19786 PORTS_CHANNEL channel ) ;
19820 PORTS_MODULE_ID index ,
19821 PORTS_CHANNEL channel ,
19857 PORTS_MODULE_ID index ,
19858 PORTS_CHANNEL channel ,
19904 PORTS_MODULE_ID index ,
19905 PORTS_CHANNEL channel ,
19907 PORTS_PIN_MODE mode ) ;
19949 PORTS_MODULE_ID index ,
19950 PORTS_CHANNEL channel ,
19993 PORTS_MODULE_ID index ,
19994 PORTS_CHANNEL channel ,
20034 PORTS_MODULE_ID index ,
20035 PORTS_CHANNEL channel ,
20075 PORTS_MODULE_ID index ,
20076 PORTS_CHANNEL channel ,
20120 PORTS_MODULE_ID index ,
20121 PORTS_CHANNEL channel ,
20165 PORTS_MODULE_ID index ,
20166 PORTS_CHANNEL channel ,
20212 PORTS_MODULE_ID index ,
20213 PORTS_AN_PIN anPins ,
20214 PORTS_PIN_MODE mode ) ;
20257 PORTS_MODULE_ID index ,
20258 PORTS_CN_PIN cnPins ) ;
20302 PORTS_MODULE_ID index ,
20303 PORTS_CN_PIN cnPins ) ;
20346 PORTS_MODULE_ID index ,
20347 PORTS_CN_PIN cnPins ) ;
20390 PORTS_MODULE_ID index ,
20391 PORTS_CN_PIN cnPins ) ;
20425 PORTS_MODULE_ID index ) ;
20458 PORTS_MODULE_ID index ) ;
20494 PORTS_MODULE_ID index ,
20495 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20531 PORTS_MODULE_ID index ,
20532 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20569 PORTS_MODULE_ID index ) ;
20603 PORTS_MODULE_ID index ) ;
20639 PORTS_MODULE_ID index ,
20640 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20676 PORTS_MODULE_ID index ,
20677 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20722 PORTS_MODULE_ID index ,
20723 PORTS_CHANNEL channel ,
20725 PORTS_PIN_SLEW_RATE slewRate ) ;
20762 PORTS_PIN_SLEW_RATE
20764 PORTS_MODULE_ID index ,
20765 PORTS_CHANNEL channel ,
20766 PORTS_BIT_POS bitPos ) ;
20805 PORTS_MODULE_ID index ,
20806 PORTS_CHANNEL channel ,
20807 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20840 PORTS_CHANGE_NOTICE_METHOD
20842 PORTS_MODULE_ID index ,
20843 PORTS_CHANNEL channel ) ;
20891 PORTS_MODULE_ID index ,
20892 PORTS_CHANNEL channel ,
20942 PORTS_MODULE_ID index ,
20943 PORTS_CHANNEL channel ,
20991 PORTS_MODULE_ID index ,
20992 PORTS_CHANNEL channel ,
20993 PORTS_BIT_POS bitPos ,
20994 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21037 PORTS_MODULE_ID index ,
21038 PORTS_CHANNEL channel ,
21039 PORTS_BIT_POS bitPos ) ;
21070 PORTS_MODULE_ID index ) ;
21094 PORTS_MODULE_ID index ) ;
21118 PORTS_MODULE_ID index ) ;
21142 PORTS_MODULE_ID index ) ;
21167 PORTS_MODULE_ID index ) ;
21192 PORTS_MODULE_ID index ) ;
21223 PORTS_MODULE_ID index ) ;
21251 PORTS_MODULE_ID index ) ;
21278 PORTS_MODULE_ID index ) ;
21303 PORTS_MODULE_ID index ) ;
21330 PORTS_MODULE_ID index ) ;
21355 PORTS_MODULE_ID index ) ;
21382 PORTS_MODULE_ID index ) ;
21407 PORTS_MODULE_ID index ) ;
21435 PORTS_MODULE_ID index ) ;
21463 PORTS_MODULE_ID index ) ;
21491 PORTS_MODULE_ID index ) ;
21517 PORTS_MODULE_ID index ) ;
21543 PORTS_MODULE_ID index ) ;
21569 PORTS_MODULE_ID index ) ;
21594 PORTS_MODULE_ID index ) ;
21620 PORTS_MODULE_ID index ) ;
21647 PORTS_MODULE_ID index ) ;
21672 PORTS_MODULE_ID index ) ;
21707 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21708 #define _PLIB_PORTS_COMPATIBILITY_H 21709 #include <stdint.h> 21710 #include <stddef.h> 21745 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21762 #include "system/int/sys_int.h" 21896 PORTS_MODULE_ID index ,
21897 PORTS_CHANNEL channel ) ;
21929 PORTS_MODULE_ID index ,
21930 PORTS_CHANNEL channel ,
21960 PORTS_MODULE_ID index ,
21961 PORTS_CHANNEL channel ) ;
21999 PORTS_MODULE_ID index ,
22000 PORTS_CHANNEL channel ,
22034 PORTS_MODULE_ID index ,
22035 PORTS_CHANNEL channel ,
22072 PORTS_MODULE_ID index ,
22074 PORTS_CHANNEL channel ,
22104 PORTS_MODULE_ID index ,
22105 PORTS_CHANNEL channel ) ;
22136 PORTS_MODULE_ID index ,
22137 PORTS_CHANNEL channel ,
22169 PORTS_MODULE_ID index ,
22170 PORTS_CHANNEL channel ,
22202 PORTS_MODULE_ID index ,
22203 PORTS_CHANNEL channel ,
22237 PORTS_MODULE_ID index ,
22238 PORTS_CHANNEL channel ) ;
22278 PORTS_MODULE_ID index ,
22279 PORTS_REMAP_INPUT_FUNCTION
function ,
22280 PORTS_REMAP_INPUT_PIN remapPin ) ;
22315 PORTS_MODULE_ID index ,
22316 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22317 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22350 PORTS_MODULE_ID index ) ;
22378 PORTS_MODULE_ID index ) ;
22412 PORTS_MODULE_ID index ,
22413 PORTS_CHANGE_NOTICE_PIN pinNum ,
22445 PORTS_MODULE_ID index ,
22446 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22475 PORTS_MODULE_ID index ) ;
22504 PORTS_MODULE_ID index ) ;
22535 PORTS_MODULE_ID index ,
22536 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22567 PORTS_MODULE_ID index ,
22568 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22607 PORTS_MODULE_ID index ,
22608 PORTS_ANALOG_PIN pin ,
22609 PORTS_PIN_MODE mode ) ;
22646 PORTS_MODULE_ID index ,
22647 PORTS_CHANNEL channel ,
22648 PORTS_BIT_POS bitPos ,
22683 PORTS_MODULE_ID index ,
22684 PORTS_CHANNEL channel ,
22685 PORTS_BIT_POS bitPos ) ;
22718 PORTS_MODULE_ID index ,
22719 PORTS_CHANNEL channel ,
22720 PORTS_BIT_POS bitPos ) ;
22753 PORTS_MODULE_ID index ,
22754 PORTS_CHANNEL channel ,
22755 PORTS_BIT_POS bitPos ) ;
22788 PORTS_MODULE_ID index ,
22789 PORTS_CHANNEL channel ,
22790 PORTS_BIT_POS bitPos ) ;
22823 PORTS_MODULE_ID index ,
22824 PORTS_CHANNEL channel ,
22825 PORTS_BIT_POS bitPos ) ;
22862 PORTS_MODULE_ID index ,
22864 PORTS_CHANNEL channel ,
22865 PORTS_BIT_POS bitPos ) ;
22898 PORTS_MODULE_ID index ,
22899 PORTS_CHANNEL channel ,
22900 PORTS_BIT_POS bitPos ) ;
22933 PORTS_MODULE_ID index ,
22934 PORTS_CHANNEL channel ,
22935 PORTS_BIT_POS bitPos ) ;
22968 PORTS_MODULE_ID index ,
22969 PORTS_CHANNEL channel ,
22970 PORTS_BIT_POS bitPos ) ;
23003 PORTS_MODULE_ID index ,
23004 PORTS_CHANNEL channel ,
23005 PORTS_BIT_POS bitPos ) ;
23038 PORTS_MODULE_ID index ,
23039 PORTS_CHANNEL channel ,
23040 PORTS_BIT_POS bitPos ) ;
23073 PORTS_MODULE_ID index ,
23074 PORTS_CHANNEL channel ,
23075 PORTS_BIT_POS bitPos ) ;
23108 PORTS_MODULE_ID index ,
23109 PORTS_CHANNEL channel ,
23110 PORTS_BIT_POS bitPos ,
23193 #ifndef _DRV_SPI_DEFINITIONS_H 23194 #define _DRV_SPI_DEFINITIONS_H 23200 #include <stdint.h> 23201 #include <stdbool.h> 23202 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23203 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23239 #ifndef _PLIB_SPI_H 23240 #define _PLIB_SPI_H 23274 #ifndef _PLIB_SPI_PROCESSOR_H 23275 #define _PLIB_SPI_PROCESSOR_H 23276 #error "Can't find header" 23321 SPI_MODULE_ID index ) ;
23351 SPI_MODULE_ID index ) ;
23383 SPI_MODULE_ID index ) ;
23415 SPI_MODULE_ID index ) ;
23449 SPI_MODULE_ID index ) ;
23479 SPI_MODULE_ID index ) ;
23516 SPI_MODULE_ID index ) ;
23555 SPI_MODULE_ID index ) ;
23585 SPI_MODULE_ID index ,
23616 SPI_MODULE_ID index ,
23650 SPI_MODULE_ID index ,
23651 SPI_COMMUNICATION_WIDTH width ) ;
23686 SPI_MODULE_ID index ,
23687 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23719 SPI_MODULE_ID index ,
23720 SPI_INPUT_SAMPLING_PHASE phase ) ;
23752 SPI_MODULE_ID index ,
23753 SPI_OUTPUT_DATA_PHASE phase ) ;
23784 SPI_MODULE_ID index ,
23785 SPI_CLOCK_POLARITY polarity ) ;
23815 SPI_MODULE_ID index ) ;
23845 SPI_MODULE_ID index ) ;
23883 SPI_MODULE_ID index ,
23884 uint32_t clockFrequency ,
23885 uint32_t baudRate ) ;
23916 SPI_MODULE_ID index ) ;
23948 SPI_MODULE_ID index ) ;
23981 SPI_MODULE_ID index ) ;
24014 SPI_MODULE_ID index ) ;
24046 SPI_MODULE_ID index ) ;
24076 SPI_MODULE_ID index ) ;
24107 SPI_MODULE_ID index ) ;
24138 SPI_MODULE_ID index ) ;
24169 SPI_MODULE_ID index ) ;
24201 SPI_MODULE_ID index ,
24202 SPI_FIFO_TYPE type ) ;
24234 SPI_MODULE_ID index ) ;
24266 SPI_MODULE_ID index ) ;
24300 SPI_MODULE_ID index ,
24301 SPI_FIFO_INTERRUPT mode ) ;
24331 SPI_MODULE_ID index ) ;
24361 SPI_MODULE_ID index ) ;
24393 SPI_MODULE_ID index ,
24394 SPI_FRAME_PULSE_DIRECTION direction ) ;
24427 SPI_MODULE_ID index ,
24428 SPI_FRAME_PULSE_POLARITY polarity ) ;
24461 SPI_MODULE_ID index ,
24462 SPI_FRAME_PULSE_EDGE edge ) ;
24495 SPI_MODULE_ID index ,
24496 SPI_FRAME_PULSE_WIDTH width ) ;
24530 SPI_MODULE_ID index ,
24531 SPI_FRAME_SYNC_PULSE pulse ) ;
24563 SPI_MODULE_ID index ) ;
24593 SPI_MODULE_ID index ) ;
24625 SPI_MODULE_ID index ) ;
24655 SPI_MODULE_ID index ) ;
24685 SPI_MODULE_ID index ) ;
24715 SPI_MODULE_ID index ) ;
24746 SPI_MODULE_ID index ,
24778 SPI_MODULE_ID index ,
24810 SPI_MODULE_ID index ,
24833 SPI_MODULE_ID index ) ;
24864 SPI_MODULE_ID index ,
24865 SPI_BAUD_RATE_CLOCK type ) ;
24897 SPI_MODULE_ID index ,
24898 SPI_ERROR_INTERRUPT error ) ;
24930 SPI_MODULE_ID index ,
24931 SPI_ERROR_INTERRUPT error ) ;
24962 SPI_MODULE_ID index ,
24963 SPI_AUDIO_ERROR error ) ;
24994 SPI_MODULE_ID index ,
24995 SPI_AUDIO_ERROR error ) ;
25025 SPI_MODULE_ID index ) ;
25055 SPI_MODULE_ID index ) ;
25087 SPI_MODULE_ID index ,
25088 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25120 SPI_MODULE_ID index ,
25121 SPI_AUDIO_PROTOCOL mode ) ;
25154 SPI_MODULE_ID index ) ;
25180 SPI_MODULE_ID index ) ;
25206 SPI_MODULE_ID index ) ;
25231 SPI_MODULE_ID index ) ;
25256 SPI_MODULE_ID index ) ;
25281 SPI_MODULE_ID index ) ;
25307 SPI_MODULE_ID index ) ;
25332 SPI_MODULE_ID index ) ;
25357 SPI_MODULE_ID index ) ;
25382 SPI_MODULE_ID index ) ;
25407 SPI_MODULE_ID index ) ;
25432 SPI_MODULE_ID index ) ;
25458 SPI_MODULE_ID index ) ;
25483 SPI_MODULE_ID index ) ;
25508 SPI_MODULE_ID index ) ;
25533 SPI_MODULE_ID index ) ;
25559 SPI_MODULE_ID index ) ;
25585 SPI_MODULE_ID index ) ;
25611 SPI_MODULE_ID index ) ;
25635 SPI_MODULE_ID index ) ;
25660 SPI_MODULE_ID index ) ;
25685 SPI_MODULE_ID index ) ;
25710 SPI_MODULE_ID index ) ;
25736 SPI_MODULE_ID index ) ;
25761 SPI_MODULE_ID index ) ;
25786 SPI_MODULE_ID index ) ;
25811 SPI_MODULE_ID index ) ;
25836 SPI_MODULE_ID index ) ;
25861 SPI_MODULE_ID index ) ;
25887 SPI_MODULE_ID index ) ;
25914 SPI_MODULE_ID index ) ;
25939 SPI_MODULE_ID index ) ;
25965 SPI_MODULE_ID index ) ;
25991 SPI_MODULE_ID index ) ;
26017 SPI_MODULE_ID index ) ;
26042 SPI_MODULE_ID index ) ;
26067 SPI_MODULE_ID index ) ;
26093 SPI_MODULE_ID index ) ;
26119 SPI_MODULE_ID index ) ;
26131 #include "system/common/sys_common.h" 26132 #include "system/common/sys_module.h" 26133 #include "system/int/sys_int.h" 26134 #include "system/clk/sys_clk.h" 26135 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26173 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26185 #define DRV_SPI_INDEX_0 0 26186 #define DRV_SPI_INDEX_1 1 26187 #define DRV_SPI_INDEX_2 2 26188 #define DRV_SPI_INDEX_3 3 26189 #define DRV_SPI_INDEX_4 4 26190 #define DRV_SPI_INDEX_5 5 26202 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26451 SPI_MODULE_ID
spiId ;
26484 CLK_BUSES_PERIPHERAL
spiClk ;
26644 const SYS_MODULE_INDEX index ,
26645 const SYS_MODULE_INIT *
const init ) ;
26687 SYS_MODULE_OBJ
object ) ;
26736 SYS_MODULE_OBJ
object ) ;
26777 SYS_MODULE_OBJ
object ) ;
26842 const SYS_MODULE_INDEX drvIndex ,
27437 #include "driver/usb/usbhs/drv_usbhs.h" 27438 #include "usb/usb_device.h" 27466 #include <stdint.h> 27486 uint8_t RevNumber ;
27573 SYS_MODULE_OBJ sysTmr ;
27574 SYS_MODULE_OBJ drvTmr0 ;
27575 SYS_MODULE_OBJ drvTmr1 ;
27576 SYS_MODULE_OBJ drvTmr2 ;
27577 SYS_MODULE_OBJ drvTmr3 ;
27578 SYS_MODULE_OBJ drvTmr4 ;
27579 SYS_MODULE_OBJ drvUsart0 ;
27580 SYS_MODULE_OBJ drvPMP0 ;
27582 SYS_MODULE_OBJ spiObjectIdx0 ;
27584 SYS_MODULE_OBJ spiObjectIdx1 ;
27586 SYS_MODULE_OBJ spiObjectIdx2 ;
27587 SYS_MODULE_OBJ drvUSBObject ;
27588 SYS_MODULE_OBJ usbDevObject0 ;
27657 bool spi_write_complete_flag ;
27658 bool spi_sent_flag ;
27659 uint16_t adj [ 1 ] ;
27662 bool new_cont_values_flag ;
27664 uint16_t cont_prev ;
27665 uint16_t cont_new ;
27669 uint16_t update_rate ;
27670 uint16_t rate_time ;
27671 uint16_t update_count ;
27675 uint16_t sensor_offset ;
27677 uint16_t sensor_constant ;
27678 uint16_t max_current ;
27679 uint16_t current_limit ;
27680 uint16_t upper_current_limit ;
27681 uint8_t over_current_count ;
27682 bool new_current_values_flag ;
27683 bool new_voltage_values_flag ;
27684 bool overcurrent_flag ;
27685 bool overvoltage_flag ;
27751 #include <stdint.h> 27752 #include <stdbool.h> 27792 uint16_t hvps_cont ;
27793 uint16_t wl_cps_i ;
27794 uint16_t wl_cps_v ;
27795 uint16_t wl_sps_i_cf ;
27796 uint16_t wl_sps_i ;
27865 #include <stdbool.h> 27866 #include "../system_config.h" 27867 #include "../system_definitions.h" 27883 #define ManHalfUpper 11800U 27884 #define ManHalfLower 2000U 27885 #define ManFullUpper 20000U 27886 #define ManFullLower 11801U 27887 #define NoManBits 32U 27888 #define HalfBit 0x12U 27889 #define FullBit 0x10U 27890 #define SizeOfBiasLUT 48U 27970 uint16_t preamble [ 5 ] ;
27971 uint16_t time [ 96 ] ;
27972 uint8_t level [ 96 ] ;
27973 uint8_t ans [ 32U + 2 ] ;
27974 uint8_t msg [ 4 ] ;
27975 uint8_t cnt_preamble ;
27976 uint8_t trynumber ;
27977 bool process_complete_flag ;
27978 bool spi_write_complete_flag ;
27979 bool spi_sent_flag ;
27980 uint8_t timer_count ;
27981 uint8_t timer_complete ;
27985 bool manual_bias_flag ;
28008 uint16_t adj [ 1 ] ;
28009 uint16_t dac_a_setting ;
28010 uint16_t dac_b_setting ;
28402 #include "../system_config.h" 28403 #include "../system_definitions.h" 28404 #include <stdbool.h> 28413 #define NEGATIVE_OFFSET 0x02U 28414 #define POS_HIGH_OFFSET 0x01U 28415 #define POS_LOW_OFFSET 0x03U 28416 #define DEFAULT_OFFSET 0x04U 28417 #define I_ARRAY_SIZE 50U 28464 uint16_t voltage_limit ;
28465 uint16_t upper_voltage_limit ;
28466 uint16_t volt_count ;
28468 uint16_t max_current ;
28469 uint16_t current_limit ;
28470 uint16_t upper_current_limit ;
28471 uint8_t over_current_count ;
28472 uint8_t array_sum_count ;
28473 uint8_t array_count ;
28475 int16_t i_array [ 50U ] ;
28477 bool new_current_values_flag ;
28478 bool new_voltage_values_flag ;
28479 bool overcurrent_flag ;
28480 bool overvoltage_flag ;
28481 uint16_t sensor_offset ;
28482 uint16_t sensor_constant ;
28483 bool sensor_offset_tick ;
28484 uint16_t v_array [ 50 ] ;
28485 uint16_t v_array_count ;
28491 uint8_t overvoltage_count ;
28619 #include "../system_definitions.h" 28669 bool spi_write_complete_flag ;
28670 bool spi_sent_flag ;
28671 uint16_t adj [ 1 ] ;
28674 bool new_cont_values_flag ;
28676 uint16_t cont_prev ;
28677 uint16_t cont_new ;
28681 uint16_t update_rate ;
28682 uint16_t rate_time ;
28683 uint16_t update_count ;
28687 uint16_t sensor_offset ;
28689 uint16_t sensor_constant ;
28690 uint16_t max_current ;
28691 uint16_t current_limit ;
28692 uint16_t upper_current_limit ;
28693 uint8_t over_current_count ;
28694 bool new_current_values_flag ;
28695 bool new_voltage_values_flag ;
28696 bool overcurrent_flag ;
28697 bool overvoltage_flag ;
28799 #include <stdbool.h> 28800 #include <stdint.h> 28832 uint8_t bitposn ) ;
28858 uint8_t bitposn ) ;
28962 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
28994 int izzqqzz=((int)(
bitmapstruct.element2 |= (1 << 0)));
29448 #define qqqbranches 141 29449 #define QQQMAXMCDCSIZE 2 29453 #define ldra_sscanf 29469 #undef qqnull_params 29470 #define qqnull_params void 29472 #define qqzzidfield 1 29478 #define QQQFIXEDSIZE 29498 qqcptr = qqscan_str;
29500 while (qqcptr[0] ==
' ')
29506 if (qqcptr[0] ==
'-')
29512 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
29514 qqvalue = 10 * qqvalue;
29515 qqvalue = qqvalue + (qqcptr[0] -
'0');
29518 qqvalue = qqisign * qqvalue;
29544 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
29545 ldra_port_write (&ldra_buffer[0]);
29553 ldra_port_write(s);
29561 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
29562 ldra_port_write (&ldra_buffer[0]);
29570 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
29571 ldra_port_write (&ldra_buffer[0]);
29579 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
29580 ldra_port_write (&ldra_buffer[0]);
29699 static int branches_printed = 0;
29703 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
29704 ldra_port_write (&ldra_buffer[0]);
29705 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
29706 ldra_port_write (&ldra_buffer[0]);
29708 branches_printed += 8;
29728 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 29729 #define LASTELEMENT 29730 #include "hvps_test_67zbelem.def" bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
void DRV_ADC0_Close(void)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
static void DRV_TMR2_Close(void)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
static void DRV_TMR3_Tasks(void)
void DRV_TMR1_PeriodValueSet(uint32_t value)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
SPI_BAUD_RATE_CLOCK baudClockSource
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void Prepare_Return_A(uint8_t byte, uint16_t data2, uint16_t data1)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
uint32_t DRV_TMR2_PeriodValueGet(void)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
void PLIB_DMA_Disable(DMA_MODULE_ID index)
uint32_t SYS_DMA_ChannelCRCGet(void)
void DRV_USART_Close(const DRV_HANDLE handle)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
void Set_Bias(uint8_t value)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
ldra_void_function qqqaccumupload[QQQnumfil]
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
static void DRV_TMR2_Tasks(void)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
static void DRV_TMR1_Tasks(void)
static void DRV_TMR2_DeInitialize(void)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
static void DRV_TMR1_DeInitialize(void)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_POLARITY framePulsePolarity
uint32_t DRV_TMR3_CounterValueGet(void)
void DRV_TMR0_CounterValueSet(uint32_t value)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR2_PeriodValueSet(uint32_t value)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
static void DRV_TMR0_Close(void)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_ERROR_LEVEL gblErrLvl
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void DRV_TMR1_CounterClear(void)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
static HVPS_TEST_STATES H_T_STATES
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
#define hvps_test_67zzopen
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
void DRV_USART0_Close(void)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
void SYS_DMA_Resume(void)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void DRV_TMR4_StopInIdleDisable(void)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
void Prepare_Return_B(uint8_t byt [])
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
static void DRV_TMR2_Open(void)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
void DRV_TMR0_StopInIdleDisable(void)
void DRV_PMP0_ModeConfig(void)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
void DRV_TMR0_PeriodValueSet(uint32_t value)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_USART_BAUD_SET_RESULT
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void DRV_TMR0_CounterClear(void)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_TMR0_CounterValueGet(void)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
static void qqqqinitialise(int ii)
bool spi_write_complete_flag
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
uint8_t jobQueueReserveSize
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
SYS_MODULE_INIT moduleInit
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR0_PeriodValueGet(void)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void Init_Manchester(void)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
static int qqqisinitialised
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
static bool Check_Manchester(void)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
static int qqqstructzzopen
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
void DRV_TMR3_StopInIdleEnable(void)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
#define DRV_IC_Close(handle)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR4_CounterClear(void)
INT_SOURCE txInterruptSource
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void qqqupload(qqnull_params)
void DRV_USART0_WriteByte(const uint8_t byte)
void DRV_USART0_TasksError(void)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool DRV_SPIn_ReceiverBufferIsFull(void)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
static SYS_STATUS DRV_TMR3_Status(void)
void DRV_TMR_Stop(DRV_HANDLE handle)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
bool DRV_TMR4_Start(void)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
void PLIB_USART_Enable(USART_MODULE_ID index)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
DRV_USART_TRANSFER_STATUS
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_DMA_CHANNEL_IGNORE_MATCH
SPI_FRAME_PULSE_DIRECTION framePulseDirection
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
void DRV_TMR1_Initialize(void)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
void DRV_ADC_Initialize(void)
void DRV_ADC1_Close(void)
static void DRV_TMR4_Close(void)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
static int hvps_test_67zqqzqz(qqnull_params)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void DRV_TMR1_CounterValueSet(uint32_t value)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static int hvps_test_67zqzqzq(int qqqi)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
uint8_t DRV_USART0_ReadByte(void)
bool DRV_IC0_BufferIsEmpty(void)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
void DRV_TMR_Close(DRV_HANDLE handle)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
SPI_FRAME_PULSE_WIDTH framePulseWidth
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void MAN_PROCESS_Tasks(void)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
void SYS_PORTS_Initialize()
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
uint8_t DRV_PMP0_Read(void)
void DRV_TMR4_StopInIdleEnable(void)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
void Set_WL_SPS_CurrentLimit(uint16_t value)
static void Flush_Buffer_Manchester(void)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
bool SYS_DMA_IsBusy(void)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
static void DRV_TMR4_Open(void)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
static SYS_STATUS DRV_TMR4_Status(void)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
void DRV_USART0_TasksReceive(void)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
void DRV_TMR4_PeriodValueSet(uint32_t value)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
DRV_SPI_BUFFER_TYPE bufferType
uint32_t DRV_TMR2_CounterFrequencyGet(void)
void SYS_DEBUG_Print(const char *format,...)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void DRV_PMP0_Write(uint8_t data)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
bool DRV_TMR0_Start(void)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
void DRV_TMR2_Initialize(void)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
uint32_t DRV_IC0_Capture32BitDataRead(void)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
uint32_t DRV_TMR4_PeriodValueGet(void)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
void DRV_TMR2_CounterClear(void)
void qqqtotalupload(void)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
SPI_FRAME_PULSE_EDGE framePulseEdge
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
static int qqqqbmselwidth
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
void DRV_TMR3_CounterClear(void)
void DRV_TMR2_CounterValueSet(uint32_t value)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
DRV_SPI_BUFFER_HANDLE bufferHandle2
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
void SYS_DMA_Suspend(void)
uintptr_t DRV_USART_BUFFER_HANDLE
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
void DRV_ADC_DeInitialize(void)
static SYS_STATUS DRV_TMR2_Status(void)
void(* ldra_void_function)()
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
bool DRV_SPIn_TransmitterBufferIsFull(void)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
void Clear_Status(uint8_t bitposn)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
struct _DRV_SPI_INIT DRV_SPI_INIT
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
CLK_BUSES_PERIPHERAL spiClk
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void Set_Status(uint8_t bitposn)
uint32_t DRV_TMR2_CounterValueGet(void)
void DRV_TMR3_Initialize(void)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
static void qqoutput2(FILEPOINT char *s, int i, int j)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
static int hvps_test_67zqendz(int qqqi)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
void DRV_TMR4_Initialize(void)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
void SPI_5_EventHandler(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
SPI_COMMUNICATION_WIDTH commWidth
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
bool DRV_TMR2_Start(void)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
static void DRV_TMR3_Open(void)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
static void qqoutput0(FILEPOINT char *s)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
static int hvps_test_67zscanf(char *qqscan_str)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool new_current_values_flag
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
DRV_USART_TRANSFER_STATUS
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void DRV_TMR1_StopInIdleDisable(void)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void DRV_TMR2_StopInIdleEnable(void)
static SYS_STATUS DRV_TMR1_Status(void)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
static void DRV_TMR4_Tasks(void)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
static void qqoutput(FILEPOINT char *s, int i)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
static float32_t Calc_Fsk_Scaling(void)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
#define DRV_IC_Open(drvIndex, intent)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
void DRV_IC0_Initialize(void)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
void DRV_TMR3_StopInIdleDisable(void)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
#define hvps_test_67zqqzqz1
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void HVPS_Test_Tasks(void)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
static void DRV_TMR3_DeInitialize(void)
void DRV_TMR0_StopInIdleEnable(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool new_cont_values_flag
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void Decode_Manchester(void)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_STATUS DRV_USART0_Status(void)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void APP_Initialize(void)
void DRV_TMR4_CounterValueSet(uint32_t value)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
static void DRV_TMR0_DeInitialize(void)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool DRV_TMR_Start(DRV_HANDLE handle)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR3_Close(void)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
static void DRV_TMR0_Tasks(void)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
uint32_t DRV_TMR4_CounterValueGet(void)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
static SYS_STATUS DRV_TMR0_Status(void)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
void DRV_TMR3_CounterValueSet(uint32_t value)
void DRV_TMR2_StopInIdleDisable(void)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
SPI_AUDIO_PROTOCOL audioProtocolMode
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
DRV_SPI_CLOCK_MODE clockMode
static void DRV_TMR0_Open(void)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void DRV_TMR1_StopInIdleEnable(void)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static unsigned char qqqzzglobflag
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
void DRV_USART0_Deinitialize(void)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
uint32_t DRV_TMR1_PeriodValueGet(void)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
void DRV_IC_Stop(DRV_HANDLE handle)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
bool DRV_TMR1_Start(void)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
void Set_HVPS_Ramp_Rate(uint16_t value)
INT_SOURCE rxInterruptSource
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR4_DeInitialize(void)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
static void DRV_TMR1_Open(void)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
void SET_WL_SPS_IOffset(uint8_t mode)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool DRV_TMR3_Start(void)
static void Package_Manchester(void)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
void PLIB_USART_Disable(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
INT_SOURCE errInterruptSource
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
ldra_void_function qqqaccumreset[QQQnumfil]
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
static void Test_Manchester(void)
uintptr_t DRV_SPI_BUFFER_HANDLE
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE bufferHandle
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
uintptr_t DRV_USART_BUFFER_HANDLE
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_TMR3_PeriodValueSet(uint32_t value)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
uint16_t DRV_IC0_Capture16BitDataRead(void)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
DRV_SPI_TASK_MODE taskMode
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
SYS_DMA_CHANNEL_CHAIN_PRIO
DRV_USART_BAUD_SET_RESULT
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
uint8_t over_current_count
static struct bitmapstruct_t bitmapstruct
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART0_TasksTransmit(void)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
static void qqqbitmapreset(qqnull_params)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
bool DRV_USART0_TransmitBufferIsFull(void)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
void Calc_Auto_Bias(void)
SPI_FRAME_SYNC_PULSE frameSyncPulse
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
uint32_t DRV_TMR1_CounterValueGet(void)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
void DRV_TMR0_Initialize(void)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
static void DRV_TMR1_Close(void)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
uint32_t DRV_TMR3_PeriodValueGet(void)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
void SYS_DEBUG_Message(const char *message)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_PMP0_Initialize(void)